Digital Signaling Methods Binary Options

Opciones binarias es una nueva manera emocionante de hacer dinero en línea, más personas de todo el mundo se están convirtiendo en comerciantes de opciones binarias. Negociar en vivo resultados del mercado día y noche. Esta evolución del comercio en línea permite a las personas a operar alrededor del reloj, independientemente de la zona horaria en que viven pulg En esta área de negocio hay una gran competencia para cada operador, las empresas de opciones binarias tratando de innovar y ofrecer nuevas características todo el tiempo para traer el Mayoría de los comerciantes a su lado. Es muy importante saber qué agente es de confianza y qué plataforma es mejor para un comerciante necesita. Signals Binario ofrece un servicio gratuito para ayudar a aquellos que optan por el comercio, y también un desglose de la comparación de corredores de las plataformas que conocemos. Las señales tienen una relación de alta precisión, pero la responsabilidad es sólo los usuarios. Se hacen muchos esfuerzos para enviar y proporcionar las mejores señales precisas. Signals Binary no puede garantizar que obtendrá ningún beneficio utilizando los métodos y las señales proporcionadas. Los ejemplos y videos mostrados en este sitio web no deben ser referidos como una promesa de ganancias. El potencial ganador / ganador y los resultados ganadores dependen totalmente del operador / usuario. Una gran cantidad de factores se incluyen en su éxito en el mercado de opciones binarias. Las señales no deben ser referidas como 100 éxito, no en ningún punto. No hay ninguna garantía de que pueda reproducir el éxito que se muestra en este sitio web. O en ese asunto cualquier otro usuario binario de señales que puede o no recomendó este sitio web para usted. JavaScript está desactivado actualmente. Los sistemas y métodos para comunicar datos digitales asociados con amplitudes y fases de una forma de onda periódica virtual que tienen un período designado entre componentes conectados por n conductores incluyen, en una Que convierte una primera amplitud y una primera fase en una primera tensión o corriente correspondiente y aplica la primera tensión o corriente correspondiente a una primera de la pluralidad de conductores y convierte la primera amplitud y la primera fase en (n1) Correspondiendo las tensiones o corrientes basadas en amplitudes de la fase de forma de onda periódica desplazada alrededor de m (360 / n) con respecto a la primera fase donde m está indexado de uno a (n1) y aplica cada tensión o corriente correspondiente a un conductor asociado de la pluralidad De conductores. Los sistemas y métodos son particularmente adecuados para reducir el número de conductores para obtener una velocidad de transferencia de datos de E / S deseada para chips de circuitos integrados y redes cableadas. 1. Procedimiento para la señalización digital sobre un grupo de n conductores, que comprende: asociar un patrón binario de bits múltiples único con coordenadas n-dimensionales únicas correspondientes para cada uno de una pluralidad de patrones que convierten cada coordenada de Las coordenadas n-dimensionales a una tensión o corriente correspondiente que comunican el patrón binario de múltiples bits aplicando cada voltaje o corriente asociado con las coordenadas n-dimensionales a un conductor correspondiente del grupo de n conductores, en el que el número n de conductores es menor Que el número de bits de cada patrón binario de múltiples bits. 2. El método de la reivindicación 1, que comprende además: decodificar el patrón binario de múltiples bits asociado con las coordenadas n-dimensionales basado en la detección de las tensiones o corrientes de los n conductores. 3. Método según la reivindicación 2, en el que la decodificación comprende: comparar las tensiones o corrientes a una pluralidad de umbrales para determinar un valor de coordenadas correspondiente y utilizar las coordenadas n-dimensionales para recuperar un patrón de bits múltiples único asociado a partir de una tabla de consulta. 4. El método de la reivindicación 1, que comprende además: codificar una corriente de coordenadas asociadas con cada conductor usando un código de línea antes de convertir las coordenadas en tensiones o corrientes correspondientes. 5. El método de la reivindicación 1 que comprende además: cambiar el conductor correspondiente asociado con una dimensión particular de las coordenadas n-dimensionales para alterar el balance de CC a través del grupo de n conductores. 6. El método de la reivindicación 1, que comprende además: controlar una serie de valores de coordenadas secuenciales asociados a cada conductor y modificar los valores de coordenadas para ajustar al menos uno de equilibrio DC, emisiones radiadas y densidad de transición asociado con la serie de valores de coordenadas secuenciales antes Convirtiendo cada coordenada a una tensión o corriente correspondiente. 7. El procedimiento de la reivindicación 1, en el que la asociación de un patrón binario de bits múltiples único comprende asignar coordenadas n-dimensionales que maximizan la distancia entre coordenadas de patrón adyacentes dentro de un intervalo de tensión o corriente designado asociado. 8. El método de la reivindicación 1, en el que los conductores comprenden conductores de impedancia adaptados. 9. El método de la reivindicación 1, en el que la comunicación del patrón binario de bits múltiples comprende la aplicación de cada voltaje o corriente a trazas conductoras en chip de un chip de circuito integrado que tiene impedancia sustancialmente igualada y que se extiende entre componentes de circuito integrado. 10. El método de la reivindicación 9, en el que las trazas conductoras en el chip se sitúan entre capas de plano de masa del chip de circuito integrado. 11. El método de la reivindicación 1, en el que el número n de conductores corresponde al número de coordenadas en cada coordenada n-dimensional. 12. El método de la reivindicación 1, en el que cada conductor tiene un conductor secundario asociado, comprendiendo además el método de aplicar una tensión o corriente inversa al conductor secundario de manera que cada conductor y su conductor secundario asociado funcionan como un par de señalización diferencial. 13. El procedimiento de la reivindicación 1, en el que cada coordenada n-dimensional incluye n componentes, cada uno correspondiente a una dimensión, y en el que la conversión comprende convertir cada componente en una tensión o corriente correspondiente. 14. El método de la reivindicación 1, en el que las coordenadas n-dimensionales son coordenadas bidimensionales que representan amplitud y fase de una forma de onda periódica que tiene un periodo de 360 ​​grados, el número n de conductores es mayor que dos y convertir cada coordenada incluye convertir el Amplitud y fase a una primera tensión o corriente, comprendiendo además el método: generar (n1) tensiones o corrientes que corresponden cada una a valores de la forma de onda periódica en fases de intervalos de aproximadamente 360 ​​/ n grados, en donde cada una de las tensiones primera o n1 Corrientes se aplica sustancialmente simultáneamente al conductor correspondiente del grupo de n conductores para cada símbolo. 15. El método de la reivindicación 14, en el que las tensiones o corrientes asociadas con cada símbolo suman sustancialmente cero. 16. El método de la reivindicación 14, en el que la forma de onda periódica comprende una sinusoide. 17. El método de la reivindicación 14, que comprende además: generar tensiones o corrientes diferenciales para al menos dos pares de conductores que comparan cada tensión o corriente diferencial con una pluralidad de umbrales para seleccionar el patrón binario de bits múltiples único correspondiente. 18. El método de la reivindicación 17, en el que el número de umbrales es menor que el número de permutaciones del patrón binario de múltiples bits. 19. El procedimiento de la reivindicación 17, en el que la comparación comprende: generar un patrón de coincidencia binaria para al menos dos pares de conductores con cada bit del patrón binario de coincidencia asociado con uno de la pluralidad de umbrales que determina el patrón binario único binario En un número de bits aser - tados en el patrón de coincidencia binaria de al menos uno de los pares de conductores. 20. El método de la reivindicación 1, en el que la asociación del patrón binario único de bits múltiples comprende la asociación de patrones binarios de tal manera que los símbolos adyacentes tienen patrones binarios que difieren sólo por un bit. 21. Un método para comunicar datos digitales entre componentes conectados por un primer, segundo y tercer conductores, que comprende: asociar los datos digitales con las coordenadas bidimensionales únicas correspondientes que representan la amplitud y la fase de una forma de onda periódica que tiene un período asociado que convierte la amplitud y la A una primera tensión o corriente correspondiente y aplicando la tensión o corriente al primer conductor que convierte la amplitud y la fase a una segunda tensión o corriente correspondiente sobre la base de un valor de la fase de la forma de onda periódica desplazada por un tercio del periodo con respecto a La amplitud y la fase y aplicar la segunda tensión o corriente correspondiente al segundo conductor y convertir la amplitud y la fase a una tercera tensión o corriente correspondiente sobre la base de un valor de la fase de forma de onda periódica desplazada en dos tercios del período con relación a La amplitud y la fase y aplicando el tercer voltaje o corriente correspondiente al tercer conductor. 22. El método de la reivindicación 21, que comprende además: comparar tensión o corriente diferencial entre pares del primer, segundo y tercer conductores a una pluralidad de umbrales para decodificar los datos digitales. 23. El método de la reivindicación 22, en el que los datos digitales comprenden una palabra binaria de bits múltiples que tiene n bits y en la que la pluralidad de umbrales es menor que 2 n. 24. El método de la reivindicación 21, que comprende además: comparar la tensión o corriente diferencial entre el primer y el segundo conductores, tercer y primer conductores y segundo y tercer conductores con una pluralidad de umbrales para generar patrones de coincidencia binarios correspondientes que tienen un bit para cada umbral y decodificación Los datos digitales basados ​​en los patrones de coincidencia binaria. 25. El método de la reivindicación 24, en el que la decodificación comprende determinar las combinaciones únicas de número de bits aser - tados para uno o más de los patrones de coincidencia binarios. 26. El método de la reivindicación 24, que comprende además recuperar datos digitales almacenados basados ​​en los patrones de coincidencia binarios. 27. El método de la reivindicación 21, en el que la primera, segunda y tercera tensiones o corrientes correspondientes suman sustancialmente cero. 28. Un sistema para comunicar datos digitales asociados con amplitudes y fases de una forma de onda periódica que tiene un periodo de 360 ​​grados entre componentes conectados por una pluralidad de n conductores, que comprende: circuitería que convierte una primera amplitud y una primera fase en una primera tensión correspondiente O corriente y aplica la primera tensión o corriente correspondiente a una primera de la pluralidad de conductores, y convierte la primera amplitud y la primera fase en (n1) tensiones o corrientes correspondientes basadas en amplitudes de la fase de forma de onda periódica desplazada aproximadamente en m 360 / n) con relación a la primera fase donde m está indexado de uno a (n1) y aplica cada tensión o corriente correspondiente a un conductor asociado de la pluralidad de conductores. 29. El sistema de la reivindicación 28, en el que las tensiones o corrientes aplicadas a la pluralidad de conductores suman sustancialmente cero. 30. El sistema de la reivindicación 28 que comprende además: circuitería que compara la tensión o corriente de cada uno de la pluralidad de n conductores con una pluralidad de umbrales y circuitería que selecciona uno de una pluralidad de datos digitales predeterminados en respuesta a una serie de umbrales excedidos . 31. El sistema de la reivindicación 30, que comprende además: circuitería que genera una tensión o corriente diferencial para más de un emparejamiento único de la pluralidad de n conductores, en el que la circuitería que compara la tensión o corriente compara la tensión o corriente diferencial. La presente descripción se refiere a sistemas y métodos para señalización digital que pueden usarse en una variedad de aplicaciones incluyendo entrada / salida de datos para chips de circuitos integrados y redes cableadas. Décadas de aumentos en la densidad de transistores en chips de circuitos integrados han superado con creces las estrategias actuales para obtener información sobre y fuera de los chips. La necesidad de tener una conexión segura y fiable bajo una amplia variedad de condiciones de funcionamiento, al tiempo que conserva la capacidad de ensamblar chips en módulos más grandes, ha colocado mínimos duros en los tamaños de las características de las conexiones de entrada / salida (E / S). Los avances en la fabricación y los materiales continúan aumentando el número de transistores que se pueden colocar en un chip a una velocidad que se acerca a la curva de Moores Law. Sin embargo, el número y el tamaño de conexiones confiables fuera del chip casi han alcanzado los límites físicos. Muchos enfoques de la técnica anterior han intentado abordar este problema. Un enfoque consiste en utilizar buses de datos / direcciones multiplexados. Sin embargo, con los microprocesadores modernos comúnmente utilizando datos de 64 bits y buses de direcciones, y algunos utilizando 128, 256 o más bits, incluso multiplexación es incapaz de mantenerse al día con el crecimiento de la potencia de procesamiento. Además, el aumento de la velocidad del procesador combinado con el uso de procesadores de múltiples núcleos ha hecho que incluso el corto tiempo requerido para multiplexar datos y direcciones sobre los mismos pines sea una operación relativamente larga o lenta en comparación con la capacidad de procesamiento del chip. Como tal, la E / S se ha convertido en el factor limitante de la velocidad o cuello de botella en el sistema. A medida que el tamaño de los componentes disminuyó, el paquete DIP omnipresente original fue reemplazado por miniDlP y, a su vez, tecnologías de montaje en superficie como SOP, TSOP, QFP, PGA, Ball-Grid Array (BGA) y otros. Intentan miniaturizar aún más las conexiones de E / S y aumentar aún más la densidad de información a través de las interfaces de chip de encendido / apagado. Además de las restricciones de empaquetamiento físico, las señales de frecuencia más alta que están más densamente empaquetadas presentan desafíos relacionados con la interferencia electromagnética y el acoplamiento cruzado de señales en chip. En particular, a medida que aumentaban las velocidades de sincronización, aumentaba el acoplamiento o la diafonía entre señales, lo que conducía a la adopción de interconexiones de pares diferenciales para transferir datos de alta velocidad. Al abordar el acoplamiento de señales o el problema de crosstalk, este enfoque requería dos conexiones de E / S para cada ruta de E / S y, por lo tanto, no contribuyó significativamente al aumento de la capacidad de E / S. XAUI, un estándar de interfaz de unidad de conexión y otros estándares de bus diferencial agrupados fueron creados para permitir un sincronismo de velocidad muy alta de la trayectoria de E / S. Sin embargo, estas normas también están alcanzando límites a medida que las velocidades de transferencia de datos se aproximan a 40 gigabits por segundo (GBPS) a 100 GBPS. Un reloj separado (típicamente 1,25 GHz o un múltiplo) sincroniza transmisores y receptores en cada extremo del bus XAUI. Pueden usarse diversos tipos de codificación, tales como la codificación 8b / 10b o 64b / 66b para ayudar en la sincronización. A medida que más y más sistemas empiezan a incorporar codificación de audio y video a la carta, es probable que incluso las combinaciones de todos los mejores enfoques actuales sean gravadas para mantener el ritmo de las demandas de ancho de banda cada vez mayores de personas, Y los procesadores que entregan los datos. Se han desarrollado varias estrategias de codificación para transmitir información a través de un canal de ancho de banda limitado. Una estrategia de codificación utilizada ampliamente en aplicaciones de radiofrecuencia (RF) se denomina Modulación de Amplitud en Cuadratura (QAM). En esta estrategia, una onda sinusoidal tiene tanto su fase como su amplitud cambiada simultáneamente para codificar la información. Un diagrama QAM tiene ejes de fase y amplitud (o Q e I), con posiciones o valores permitidos designados (también denominados estaciones) para combinaciones de fase / amplitud que definen una constelación QAM. La estrategia QAM puede referirse a un número entero que corresponde al número de estaciones en la constelación. Como tal, una estrategia de QAM que tiene un número arbitrario N de estaciones en su constelación puede denominarse generalmente nQAM. Por ejemplo, puede representarse un nQAM típico con estaciones N16 en su constelación (16QAM) como se ilustra en la FIG. 1. El eje vertical representa el valor Q (Cuadratura o Fase) de la onda sinusoidal modulada mientras que el eje horizontal representa el valor I (En fase o Amplitud). Cada estación, representada generalmente por la estación 20. Dentro de la constelación 30 se asigna un valor que representa los bits 32 transmitidos cuando se visita dicha estación. En el ejemplo ilustrado en la Fig. 1. cada estación 20 representa cuatro (4) bits de 0000 a 1111. Mientras que un patrón particular de bits 32 puede ser asignado a cualquier estación 20. Las estaciones se disponen y numeran típicamente utilizando un código GRAY de tal manera que sólo se producen cambios de bit único entre estaciones adyacentes. Por ejemplo, la estación 24 tiene un patrón de bits asociado 34 de 0101. La estación adyacente 26 tiene un patrón de bits asociado 36 de 0100 que difiere del patrón de bits 34 por un solo bit. De forma similar, la estación adyacente 28 tiene un patrón de bits asociado 38 de 0001 que difiere del patrón de bits 34 por un solo bit. Las implementaciones convencionales de una estrategia de codificación de QAM para transferir datos utilizan una onda senoidal de base con uno o más dispositivos para proporcionar una modificación casi instantánea de la fase y / o amplitud de la onda sinusoidal para la transición de una estación de constelación a otra. Una técnica genera ondas seno y coseno de fase bloqueada, utilizando el valor Q para modular la amplitud de la onda coseno, y el valor I para modular la amplitud de la onda sinusoidal. Las dos ondas se combinan entonces utilizando un mezclador para crear la salida de RF transmitida. El ancho de banda del canal requerido para transmitir los datos está determinado por la tasa de símbolos y el teorema de Nyquists. Se pueden transferir múltiples flujos simultáneos de información utilizando transmisores / receptores de banda ancha en combinación con múltiples ondas senoidales de portadoras centrales de diferentes frecuencias, separadas por al menos el ancho de banda de cada flujo de información individual. Los aumentos recientes en la demanda de ancho de banda de Internet para el hogar han gravado los límites de las técnicas de modulación anteriores sobre los cables de cobre de par trenzado omnipresentes utilizados para la entrega de POTS (Plain Old Telephone Service). La Unión Internacional de Telecomunicaciones (UIT) ha respondido a esta rápida aceleración de la demanda de ancho de banda mediante la promulgación de normas que siguen evolucionando. Comenzando con DSL, los estándares que proporcionan entrega de ancho de banda adicional incluyen VDSL (G993.1) y VDSL2 (G993.2). Estos estándares utilizan hilos RF de RF sobre hilos de cobre de par trenzado en combinación con técnicas de codificación tales como QAM para crear múltiples bandas de abonado sobre un solo par trenzado. Mientras que tales estándares se están utilizando para tratar las demandas del ancho de banda de líneas multi-gota de una oficina central o de un headend que da servicio a varios suscriptores, son excesivamente complejos y no actualmente prácticos para los sistemas digitales típicos donde la mayor parte de la información se transfiere punto a punto Con fan-out manejado por nodos dedicados en lugar de líneas multi-drop (por ejemplo, tarjeta única o tarjetas interconectadas en backplane, o redes de cable y hub). A velocidades muy altas, los talones asociados con múltiples oyentes se vuelven difíciles de manejar, y las reflexiones de línea, el ruido acoplado y otros problemas impulsan rápidamente sistemas de datos de alta velocidad a diseños de punto a punto de malla completa. Además, el intento de reducir el tamaño de los codificadores, transmisores, receptores y decodificadores requeridos para sistemas VDSL y / o VDSL2 para que puedan ser utilizados como interfaces genéricas de chip a chip es más que problemático. Los sistemas digitales son propensos a emisiones espectrales significativas, especialmente a medida que las tasas de procesador y de datos han seguido aumentando. Para reducir significativamente las emisiones, muchos diseños modernos usan la señal diferencial de pares y ejecutan los pares diferenciales para XAUIs y otras conexiones de alta velocidad en capas interiores de un chip o tarjeta intercalados entre planos de tierra y / o voltaje para garantizar emisiones radiadas bajas de las líneas de alta velocidad . Las emisiones radiadas se generan en respuesta a los transitorios de conmutación. Por ejemplo, cuando un bit en un circuito integrado CMOS cambia de estado de 0 a 1 o de 1 a 0, la naturaleza del diseño de circuito da lugar a un breve momento cuando hay un flujo de corriente relativamente alto desde la energía a tierra, Actual (y emisiones) pico. Los periodos de conmutación también representan la mayor parte de la potencia consumida en circuitos integrados CMOS. Esto es cierto incluso para pares diferenciales, donde los dos hilos se cambian a estados opuestos. Durante la transición, hay transientes de alta tensión y corriente en ambos hilos. Con una conmutación perfecta estos transitorios estarían exactamente sincronizados y de signo opuesto y aún cancelarían en el campo lejano. Desafortunadamente, la conmutación rara vez es perfecta, de modo que los transitorios de conmutación irradian incluso de pares diferenciales bien adaptados. Como tal, la presente descripción reconoce la necesidad de aumentar la capacidad de las E / S de circuito integrado existentes sin consumir recursos significativos en el chip o presupuestos de potencia, y sin un aumento significativo de las emisiones radiadas. En una realización, un método para comunicar datos digitales entre componentes conectados por un primer, segundo y tercer conductores incluye asociar los datos digitales con las coordenadas bidimensionales únicas correspondientes que representan la amplitud y la fase de una forma de onda periódica que tiene un periodo de 360 ​​grados, Amplitud y la fase a una primera tensión o corriente correspondiente y aplicar la tensión o corriente al primer conductor, convertir la amplitud y la fase a una segunda tensión o corriente correspondiente basada en un valor de la fase de forma de onda periódica desplazada en 120 grados con relación a La amplitud y la fase y aplicar la segunda tensión o corriente correspondiente al segundo conductor y convertir la amplitud y la fase en una tercera tensión o corriente correspondiente basada en un valor de la fase de onda periódica desplazada en 240 grados (o equivalentemente 120 grados ) Con respecto a la amplitud y la fase y aplicando la tercera tensión o corriente correspondiente al tercer conductor. El método también puede incluir la comparación del voltaje o corriente diferencial entre pares del primer, segundo y tercer conductores a una pluralidad de umbrales para decodificar los datos digitales. En diversas realizaciones, los datos digitales comprenden una palabra binaria de múltiples bits que tiene n bits y la pluralidad de umbrales es menor que 2 n. Varias realizaciones pueden incluir comparar la tensión o corriente diferencial entre el primer y el segundo conductores, el primer y tercer conductores, y el segundo y tercer conductores con una pluralidad de umbrales para generar patrones de coincidencia binarios correspondientes que tienen un bit para cada umbral y decodificar los datos digitales basados ​​en Los bits aser - tados para los patrones de coincidencia binarios, que pueden incluir decodificar los datos digitales basados ​​en el número mínimo y máximo de bits aser - tados de los patrones de coincidencia para un período de símbolo particular. Los datos digitales pueden determinarse recuperando datos digitales almacenados basados ​​en los patrones binarios de coincidencia. En varias realizaciones, la primera, segunda y tercera tensiones o corrientes correspondientes suman sustancialmente cero. Las realizaciones de acuerdo con la presente descripción también pueden incluir un sistema para comunicar datos digitales asociados con amplitudes y fases de una forma de onda periódica que tiene una periodicidad especificada, tal como un periodo de 360 ​​grados, entre componentes conectados por una pluralidad de n conductores que tienen circuitos que convierten Una primera amplitud y una primera fase a una primera tensión o corriente correspondiente y aplica la primera tensión o corriente correspondiente a una primera de la pluralidad de conductores y convierte la primera amplitud y la primera fase en (n1) tensiones o corrientes correspondientes basadas En amplitudes de la fase de forma de onda periódica desplazada alrededor de m (periodo / n) con respecto a la primera fase donde m está indexado de uno a (n1) y aplica cada tensión o corriente correspondiente a un conductor asociado de la pluralidad de conductores. En diversas realizaciones, las tensiones o corrientes aplicadas a la pluralidad de conductores suman sustancialmente cero. Las realizaciones pueden incluir un circuito que compara el voltaje o corriente de cada uno de la pluralidad de n conductores con una pluralidad de umbrales y circuitería que selecciona uno de una pluralidad de datos digitales predeterminados en respuesta a un número de umbrales excedidos. Las realizaciones también pueden incluir circuitería que genere una tensión o corriente diferencial para cada par único de la pluralidad de n conductores, donde el circuito que compara el voltaje o la corriente compara la tensión o corriente diferencial con cada uno de la pluralidad de umbrales. En otras realizaciones, un método para la transferencia de datos de chip de circuito integrado incluye asociar un único patrón binario de bits múltiples con coordenadas n-dimensionales únicas correspondientes para cada uno de una pluralidad de patrones, convertir cada coordenada de las coordenadas n-dimensionales en un voltaje correspondiente o Corriente y comunicar el patrón binario de múltiples bits aplicando cada voltaje o corriente asociado con las coordenadas n-dimensionales a un conductor correspondiente de un grupo de n conductores del chip de circuito integrado, donde el número n de conductores es menor que el número De bits de cada patrón binario de múltiples bits. El método también puede incluir la decodificación del patrón binario de múltiples bits asociado con las coordenadas n-dimensionales basado en la detección de los voltajes o corrientes de los n conductores. En varias realizaciones, el método incluye comparar las tensiones o corrientes a una pluralidad de umbrales para determinar un valor de coordenadas correspondiente, y usar las coordenadas n-dimensionales para recuperar un patrón de bits múltiples único asociado a partir de una tabla de consulta. El método también puede incluir la codificación de un flujo de coordenadas asociadas con cada conductor usando un código de línea (tal como la codificación 8b / 10b) antes de convertir las coordenadas en tensiones o corrientes correspondientes. Varias realizaciones del método pueden incluir cambiar el correspondiente conductor asociado con una dimensión particular de las coordenadas n-dimensionales para alterar el balance de CC a través del grupo de n conductores. En una realización, un método para la señalización digital de acuerdo con la presente descripción incluye el monitoreo de una serie de valores de coordenadas secuenciales asociados con cada conductor y la modificación de los valores de coordenadas para ajustar al menos uno de equilibrio DC, emisiones radiadas y densidad de transición asociada con la Serie de valores de coordenadas secuenciales antes de convertir cada coordenada a una tensión o corriente correspondiente. Varias realizaciones de un método de acuerdo con la presente descripción pueden incluir la asignación de coordenadas n-dimensionales que maximizan la distancia entre coordenadas de patrón adyacentes dentro de un intervalo de voltaje o corriente asociado del chip de circuito integrado. En varias realizaciones de circuito integrado, sistemas o métodos de acuerdo con la presente descripción pueden incluir comunicar el patrón binario de múltiples bits aplicando cada voltaje o corriente a trazas conductoras en chip que tienen impedancia sustancialmente igualada y que se extienden entre componentes de circuito integrado. En algunas realizaciones, las trazas conductoras en chip se sitúan entre capas conductoras del chip de circuito integrado que pueden ser capas de planos de masa, por ejemplo. Otras realizaciones de sistemas o métodos de acuerdo con la presente descripción tienen un número n de conductores que corresponde al número de coordenadas en cada coordenada n-dimensional. En una realización, cada coordenada n-dimensional incluye n componentes cada uno correspondiente a una dimensión, y la conversión incluye convertir cada componente en una tensión o corriente correspondiente. En varias realizaciones, las coordenadas n-dimensionales son coordenadas bidimensionales que representan la amplitud y la fase de una forma de onda periódica, tal como una sinusoide, por ejemplo, que tiene un periodo designado, tal como 360 grados por ejemplo, el número n de conductores es mayor Y la conversión de cada coordenada incluye la conversión de la amplitud y la fase a una primera tensión o corriente. El método también puede incluir generar (n1) tensiones o corrientes que corresponden a valores (o amplitudes) de la forma de onda periódica en fases de intervalos de aproximadamente periodo / n grados en los que cada una de las tensiones o corrientes primera o n1 se aplica sustancialmente simultáneamente a El conductor correspondiente del grupo de n conductores. En diversas realizaciones, las tensiones o corrientes diferenciales para cada par de los conductores se comparan con una pluralidad de umbrales para seleccionar el patrón binario de bits múltiples único correspondiente. En una realización, el número de umbrales es menor que el número de permutaciones del patrón binario de múltiples bits. Las realizaciones pueden incluir generar un patrón de coincidencia binario para cada par de conductores con cada bit del patrón de coincidencia binario asociado con uno de la pluralidad de umbrales y determinar el patrón binario único de bits múltiples correspondiente basado en un número máximo y mínimo de patrones de coincidencia Bits en los patrones binarios de coincidencia de todos los pares de los conductores. Las realizaciones también pueden incluir asociar los patrones binarios de bits múltiples únicos con coordenadas n-dimensionales de tal manera que los símbolos adyacentes tengan patrones binarios que difieren sólo por un bit. Varias realizaciones de acuerdo con la presente descripción pueden proporcionar una serie de ventajas. Por ejemplo, los sistemas y métodos de acuerdo con la presente descripción facilitan un aumento sustancial de la capacidad de entrada / salida de diversas aplicaciones de comunicación / redes cableadas que incluyen circuitos integrados, tales como microprocesadores, sin consumir recursos significativos en el chip o presupuestos de potencia. Varias realizaciones de acuerdo con la presente descripción pueden proporcionar un orden de magnitud o más aumento en las velocidades de datos de E / S sobre los buses de chip a chip sin un aumento en el número de pines o aumentos significativos en el presupuesto de potencia. Como tal, las realizaciones de la presente descripción facilitan un aumento significativo de la anchura de banda disponible de chip a chip o componente a componente, con un aumento significativo asociado de la capacidad de procesamiento de microprocesadores y otros circuitos integrados. Varias realizaciones de acuerdo con la presente invención transmiten múltiples bits de información usando un solo símbolo representado por coordenadas n-dimensionales, lo que facilita una reducción en las tasas de borde de señal y una reducción correspondiente en emisiones radiadas. Algunas realizaciones permiten que sólo un alambre de un grupo o grupo cambie de estado a la vez, lo que también puede reducir las emisiones radiadas. Las realizaciones pueden incluir un cable o conductor de tierra asociado con cada grupo de señalización de conductores para reducir o eliminar el acoplamiento de señales entre los grupos de señalización adyacentes. Las realizaciones de acuerdo con la presente descripción se refieren al cuello de botella de E / S encontrado por sistemas paralelos de alta velocidad y proporcionan un camino hacia delante que debería eliminar el tamaño de la almohadilla de entrada / salida para que sea el factor limitante para el circuito integrado I / O en el futuro previsible. Además, varias realizaciones de acuerdo con la presente descripción proporcionan un marco general para la señalización digital sobre múltiples conductores que pueden reducir el consumo de potencia y las emisiones radiadas para la transferencia de datos digitales de alta velocidad en una amplia variedad de aplicaciones. BREVE DESCRIPCIÓN DE LOS DIBUJOS La FIG. La figura 1 ilustra un diagrama de constelación bidimensional para una realización de 16 símbolos de un sistema o método de acuerdo con la presente descripción. La figura 2 ilustra un diagrama de constelación bidimensional para una realización de símbolo 32 de un sistema o método de acuerdo con la presente descripción. La figura 3 ilustra una forma de onda periódica virtual representativa que tiene un periodo designado de 360 ​​grados además de las versiones desfasadas de la forma de onda para su uso en la generación de voltajes o corrientes que representan datos digitales en diversas realizaciones de un sistema o método de acuerdo con la presente descripción. La Figura 4 ilustra formas de onda periódicas virtuales representativas que tienen un periodo designado de 360 ​​grados y amplitudes diferentes para su uso en la generación de voltajes o corrientes que representan datos digitales en diversas realizaciones de un sistema o método de acuerdo con la presente descripción. Las Figuras 5A-5D ilustran disposiciones representativas para clusters de señalización de tres conductores para señalización de E / S usando señalización cableada multifásica de acuerdo con diversas realizaciones de la presente descripción. 6 es un diagrama que ilustra una realización representativa de un dispositivo de transmisión que incluye circuitería para señalización cableada multifásica de acuerdo con la presente descripción. 7 ilustra otra realización representativa de un dispositivo de transmisión que utiliza puertas de transmisión CMOS para señalización cableada multifásica de acuerdo con la presente descripción. 8 es un diagrama que ilustra una realización representativa de una circuitería para generar una tensión diferencial en un dispositivo receptor / detector para señalización cableada multifásica de acuerdo con la presente descripción. 9 is a diagram illustrating a representative embodiment of circuitry for comparing voltages to a plurality of thresholds and generating a binary match pattern for a receiver/detector device for multi-phase wired signaling according to the present disclosure FIGS. 10A-10C illustrate operation of a system or method for decoding data in response to received differential voltages/currents in a tri-phase wired signaling strategy according to various embodiments of the present disclosure FIGS. 11A-11C illustrate operation of a system or method for decoding data in response to received differential voltages/currents in a quad-phase wired signaling strategy according to various embodiments of the present disclosure and FIGS. 12 and 13 are diagrams illustrating operation of various representative embodiments of a system or method for digital signaling according to the present disclosure. Detailed embodiments of the present invention are disclosed herein however, it is to be understood that the disclosed embodiments are merely exemplary of the invention that may be embodied in various and alternative forms. The figures are not necessarily to scale some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. HIGO. 1 illustrates a constellation diagram for a 16-symbol embodiment of a system or method for digital signaling that may be used for integrated circuit chip input/output according to the present disclosure. While described above with reference to use in an RF implementation that may be transmitted over a twisted pair, for example, a similar constellation diagram may be used to implement poly-phase or multi-phase wired N-symbol signaling according to various embodiments of the present disclosure. As described in greater detail herein, embodiments according to the present disclosure use n-symbol signaling, such as represented by the 16-symbol constellation 30 of FIG. 1. to code the stations or symbols using voltage/current changes among a group of signaling conductors. For example, a typical N-symbol or N-QAM strategy with N16 stations or symbols in its constellation may be represented as illustrated in FIG. 1. The stations are arranged within an n-dimensional coordinate system, which is a 2-dimensional coordinate system in this example. While the selected coordinate system and labeling is independent of the invention as described herein, it is useful to explain operation of representative embodiments using the nomenclature and two-dimensional coordinate system of traditional QAM signaling. As described below, particular applications or implementations may select or position the stations/symbols to provide desired system operating characteristics. As illustrated in FIG. 1. the vertical axis may be thought of as representing the Q (Quadrature or Phase) value of a modulated sine wave while the horizontal axis may be thought of as representing the I (In-phase or Amplitude) value. Each station, generally represented by station 20 . within the constellation 30 is assigned digital data represented by multiple-bit binary pattern 32 that can be considered to be transmitted when the station is visited. As described in greater detail herein, the station or symbol coordinates are communicated between a transmission/encoding device and a receiving/decoding device such that the digital data is recovered from the station/symbol location or coordinates. In the example illustrated in FIG. 1. each station 20 has an associated unique multiple-bit binary pattern 32 with four (4) bits. In a 4-bit strategy, there are 2 4 or 16 permutations or bit patterns that vary from 0000 to 1111. While a particular pattern of bits 32 may be assigned to any station 20 . various advantages with respect to error detection and correction may be obtained if the stations are arranged and numbered using a gray code such that only single-bit-changes occur between adjacent stations. For example, station 24 has an associated bit pattern 34 of 0101. Adjacent station 26 has an associated bit pattern 36 of 0100 that differs from bit pattern 34 by a single bit. Similarly, adjacent station 28 has an associated bit pattern 38 of 0001 that differs from bit pattern 34 by a single bit. Conventional QAM modulates a base or carrier sine wave using one or more devices to provide near-instantaneous modification of the phase and/or amplitude of the sine wave to transition from one constellation station to another. One technique generates phase-locked sine and cosine waves, using the Q value to modulate the amplitude of the cosine wave, and the I value to modulate the amplitude of the sine wave. The two waves are then combined using a mixer to create the modulated radio frequency (RF) output that is transmitted between sending and receiving stations. The channel bandwidth required for transmitting the data is determined by the symbol rate and Nyquists theorem. Transmitting data using conventional N-QAM over conductors arranged as a differential pair in the digital world would require transmitting a differential sine wave signal of sufficiently high frequency that the N-QAM modulation-induced bandwidth remains well above DC. For a 10 gigabit-per-second data rate, using 256-QAM to encode eight bits per symbol, a symbol rate of 1.25 GHz is required, requiring a multi-gigahertz carrier (and inverse) whose phase is precisely controlled. The existing XAUI interfaces achieve this bit rate by using a 64-bit parallel bus clocked at 156.25 MHz. However, transmitting a modulated carrier which contains this information density would require a much higher line frequency. As the current signaling strategies are already approaching physical limits for wire-based frequencies, increasing the base frequency significantly above the current bit rates is not a practical solution. As recognized by the present disclosure, instead of transmitting a modulated carrier in a differential pair implementation, in various embodiments the Q-axis station coordinate may be represented by the voltage or current on one of the pair of conductors or wires, and the I-axis coordinate may be represented by the voltage or current on the other of the pair to encode a quasi-QAM signal as a pair of voltages or currents on corresponding conductors of the differential pair. In a 16-symbol constellation, each group of four bits may be encoded by voltage/current values representing the coordinates or location of the symbol/station in the constellation, with one dimension represented by the voltage/current on the Q-conductor, and the other dimension represented by the voltage/current on the I-line. Those of ordinary skill in the art will recognize that the voltages or currents can be coupled onto the respective conductors using well-known circuitry/electronics. For example, a voltage-follower design or switchable current-source design may be used to apply the corresponding voltage or current, respectively. A separate clock that identifies symbol intervals may be used to synchronize the devices at each end of the conductors to synchronize transmitters and receivers. This approach of representing the symbol or station location on the Q and I axes from a QAM constellation by a voltage (or current) of a pair of conductors can be generalized or extended to multiple conductors associated with stations arranged within an n-dimensional coordinate system. For example, the signaling strategy described above can be extended to a three-dimensional N-symbol constellation by adding a third conductor to communicate voltage or current states associated with the third dimension or coordinate component of a particular symbol/station. Similarly, a four-dimensional system or method can be used with four conductors each assigned to one dimension of the coordinates, and so on. In a four-wire system with only four voltage or current states per wire, this strategy can transmit one eight-bit symbol per transition, using only four conductors as compared to the 16 conductors required by an eight-bit XAUI interface. As recognized by the present disclosure, this signaling strategy raises potential issues with respect to practical implementations, such as generating precision voltages or currents to represent the different stations and corresponding locations/coordinates within the constellation. Likewise, similar to traditional differential pair signaling strategies that use capacitive coupling to apply the signals to the conductors, continuous transmission of a single bit value could saturate the coupling capacitors at either end of the pair. As such, encoding methods such as 8b/10b or similar line coding techniques with embedded commands may be used to allow bit randomization/inversion to avoid these conditions. Furthermore, differential pairs are used in many conventional strategies because the EM fields from the pair self-cancel in the far field if impedance is correctly controlled and wire lengths match closely. While the signaling strategy described above does not utilize a traditional differential pair, the radiated emissions may be managed and may be acceptable for many applications as described below. As long as the stations in the constellation represent voltages which are offset by easily-generated gaps (e. g. on the order of a diode-drop), those of ordinary skill in the art may recognize that generating precision voltage/current references on both transmit and receive devices is fairly straight-forward. While thermal gradients between transmit and receive devices may impact the matching from device to device, protocols analogous to line coding protocols such as 8b/10b, 64b/66b, or Transition Minimized Differential Signaling (TMDS), for example, can be used to send packets of data which exercise the full range on the transmitter so the receiver can perform local calibration and adjust to drift across time/temperature. If stations represent currents rather than voltages, precision current sources can be provided that are summed through a precision Norton-style amplifier to create the pin or conductor current. Analogous encoding methods can be used for data transport and similar calibration and drift compensation can be done in a current-based design. Driver design has already been briefly described. In one implementation, a bank of precision voltages is generated, and a low-impedance-output, high-impedance-input voltage-follower is switched via pass-gates from one voltage to another by a decoder fed by the bits which control that particular pin/conductor from the set of bits associated with the currently transmitting symbol. The follower is designed to generate an edge compliant with design specifications that may vary by application or implementation. In XAUIs and similar capacitive-coupled data transfer systems, encoding strategies such as 8b/10b or 64b/66b are used for the data to control DC balance, emissions, transition density, etc. To provide desired DC balance, a given wire should transition from one sign to the opposite sign regularly, similar to a differential pair design. However, in contrast to the XAUI and similar implementations, in systems and methods for digital signaling according to various embodiments of the present disclosure, the capacitors are no longer switching between fully charged and discharged states. Rather, the capacitors are switching between rates of charging and discharging. A similar encoding system can readily be used in various embodiments according to the present disclosure that monitor the transmitted bit stream and shuffle bit order, bit encoding, etc. to maintain DC balance, emissions, effective transition density, etc. analogous to the 8b/10b, 64b/66b, and other line coding or encoding systems familiar to those of ordinary skill in the art. In one embodiment, DC balance across the conductors within a particular signaling group is managed by changing the corresponding conductor associated with a particular dimension of the n-dimensional coordinates. For example, in a 4-wire (4-dimensional) implementation with each station/symbol having coordinates associated with a 4-dimensional coordinate or 4-tuple vector such as lta, b,c, dgt, the dimension or component (such as a) communicated by a particular conductor c 1 can be periodically changed (switched to one of the b, c, or d components) to manage DC balance across all wires. Digital systems are prone to significant spectral radiated emissions, especially as processor and data rates have continued to increase. To reduce emissions, many modern designs run differential pairs for XAUI and other high speed connections on interior layers of a card or circuit board, with ground and/or voltage planes above and below the pairs to reduce radiated emissions from the integrated circuit chip. This technique can be used with the signaling strategies according to various embodiments of the present disclosure as well to manage emissions by placing the signaling conductors between conductive ground or voltage planes of the integrated circuit chip or system card/circuit board. Emissions are also related to the edge speeds of the transmitted signals. The signaling strategy according to various embodiments of the present disclosure permits transmission of multiple bits per symbol, i. e. voltage change on one or more wires. As such, the signaling strategy of various embodiments according to the present disclosure facilitates reduced symbol rates and associated reduction in edge rates and radiated emissions. Those of ordinary skill in the art will recognize that drivers have already been designed to drive specified loads with guaranteed edge rates. As such, the voltage-follower approach described above as a representative driver implementation for a signaling strategy as described herein is a straight-forward modification of existing designs. Radiated emissions can also be managed by limiting or restricting voltage/current transitions to one conductor at a time within a cluster of signaling conductors, i. e. adjacent symbol coordinates vary by only a single dimension. Embodiments that operate with such a constraint may have advantages with respect to error detection and correction and/or better noise immunity. For example, embodiments that use this strategy have the advantage on the receiver side of being able to assume that any voltage/current change in the stable or unchanging conductor(s) maps to a common-mode change in the conductor that is anticipated to change voltage/current levels. This is generally a valid assumption as most transients common-mode couple onto adjacent conductors. In a 256-symbol system, this means that a symbol-change effectively transmits only four bits of information because from any given station, the next symbol must be adjacent, i. e. the subsequent symbol can only be a side-to-side or up-and-down station movement depending on which conductor is scheduled to move during the current symbol window or time interval. Finally, in the layout of the signaling conductors, a ground conductor can be incorporated into each symbol-carrying conductor cluster. This will reduce or prevent coupling of signals from the outside conductor(s) of a cluster to the outside conductor(s) of an adjacent cluster. As those of ordinary skill in the art may recognize, managing radiated emissions may be the most difficult challenge for the signaling method described above that assigns and uses a conductor for each coordinate of the symbol in a particular signaling constellation because there is no longer a true differential pair whose EM emissions cancel in the far field. For lower data rates, however, this strategy may be sufficient for a number of applications and offers enormous potential for bandwidth gain across existing I/O boundaries with low circuit-area impact on the transmit/receive sides of the boundary. Differential signaling could also be employed without loss of generality where each differential pair transmits a positive and a negative signal value for the given symbol coordinate dimension. While this would double the number of conductors needed relative to a single conductor per dimension, the bandwidth increase by using the non-binary encoding still reduces the total number of conductors relative to various prior art implementations. Those of ordinary skill in the art will recognize that the standard oscilloscope-based eye diagram for determining signal quality is no longer available as an analysis tool for signaling strategies according to various embodiments of the present disclosure. Rather, a plot of the constellation points or symbol coordinates over a long dwell with every constellation point visited may be used to determine the system fidelity. Systems with high fidelity will exhibit a smaller variance around the ideal symbol coordinates whereas lower fidelity will result in a constellation diagram having broad/blurry/smeared symbol points or stations. Multi-Phase Wired n-Symbol Signaling As recognized by the present disclosure, switching transients are a significant source of radiated emissions from digital equipment. As a bit on a CMOS integrated circuit changes state from 0 to 1 or from 1 to 0, the nature of the design has a brief moment when there is a relatively high current path from power to ground, resulting in a current spike and associated emissions. This occurs even on differential pairs, where the two conductors are substantially simultaneously switched to opposite states. During the transition, there are high voltage and current transients in both conductors. With ideal switching, these transients would be exactly synchronized and have opposite sign/sense such that they would cancel in the far field. In actual implementations, however, switching is rarely perfect and the switching transients result in radiated emissions, even from well-matched differential pairs. As also recognized by the present disclosure, power generation companies have long used three-phase conductors for long-distance power transmission, with each conductor carrying a voltage or current that is 120 phase advanced or retarded relative to an adjacent conductor. For a three-wire/conductor cluster, relative phasing of 0, 120, and 240, or alternately, 0, 120, and 120 may be used. Analysis of this power transmission strategy reveals that power per unit time is constant as long as demand on each conductor is identical. The present disclosure also recognizes that the bulk of the power consumed in CMOS integrated circuits implementing traditional signaling strategies is associated with switching between states. The voltage across the CMOS device remains fairly constant (with good capacitive decoupling), but very large current transients occur at every gate that changes binary state. As such, the ability to use wired n-symbol signaling with more than two conductors may be used to advantage in various embodiments according to the present disclosure to create a system having the capability to transmit data from one device to another device using near constant power and near zero radiated emissions. With careful design, switching transients associated with transitions from one transmitted symbol to another, and power fluctuations on either the transmitter or the receiver can be reduced or eliminated. While currently suitable for a wide variety of I/O applications, including integrated circuit chip and microprocessor I/O, the polyphase signaling strategy of various embodiments of the present disclosure may also be used internally within an integrated circuit chip as die-shrink continues to enable miniaturization of more complex devices. In addition, appropriate selection and design of transmitter/receiver drivers may also facilitate lower total power consumption relative to existing I/O signaling strategies. HIGO. 2 illustrates a two-dimensional constellation diagram 200 for a 32-symbol embodiment of a system or method according to the present disclosure. The two-dimensional coordinate system illustrated in FIG. 2 continues to use QAM nomenclature without loss of generality. Constellation diagram 200 includes 32 symbols or stations 210 . In the representative embodiments described below, the symbol or station coordinates can be represented by an I-axis coordinate that may also represent amplitude of a periodic (virtual) waveform used to encode or determine transmitted voltage/current values, analogous to a QAM signal if the data were being transmitted via a modulated RF sine wave. Those of ordinary skill in the art will recognize that the periodic waveform having a period of 360 is used only to determine values for the polyphase signaling strategy and that the waveform is not a physical signal. Rather, the values determined using the periodic waveform may be stored in a look-up table, or may be hard-coded or firm-coded in a gate array and/or by corresponding selection of component values used in the transmit/receive driver circuitry. Because the periodic waveform is used only to determine the signaling voltage/current values for each conductor within a signaling cluster of conductors and is not actually transmitted as a signal on any of the conductors, the periodic waveform is referred to as a virtual waveform. In the embodiment illustrated in FIGS. 2-4. a sinusoidal waveform is used and referred to as a virtual sine wave (VSW). Similarly, without loss of generality and continuing the use of QAM nomenclature, the other coordinate axis may be designated the Q-axis and may be thought of as analogous to the phase that the VSW would have if it were actually transmitted in a conventional RF QAM strategy. As previously described and illustrated in the constellation diagram 200 of FIG. 2. each symbol or station 210 has associated n-dimensional coordinates 214 that may be represented by an I-component and a Q-component in a rectilinear coordinate system, for example. Alternatively, the location or coordinates of each symbol may be expressed as an n-tuple vector having a magnitude (or amplitude) and phase angle. For example, symbol 220 may be identified by an n-tuple lt1.0,0gt having a first component 1.0 representing an amplitude, and a second component 0 representing a phase or phase angle. The amplitude and phase (or other coordinate representation) may be used to specify a first voltage/current value corresponding to a point on the periodic waveform, or VSW in this example, that is then used to determine or generate additional voltages/currents based on phase shifted values of the period waveform for each of the conductors within the signaling cluster as described in greater detail below. As with the constellation diagram of FIG. 1. each station or symbol 210 in the constellation diagram 200 of FIG. 2 includes associated digital data, represented by a unique multiple-bit binary pattern 222 . that is communicated to, and decoded by, the receiver via detection of the associated symbol coordinates. In the representative constellation diagram 200 . the 32 symbols 210 are arranged generally symmetrically and spaced at 45 degree intervals with unique multiple-bit binary patterns 222 assigned using a gray code such that only a single bit changes between two adjacent symbols. For example, binary pattern 224 (11010) differs by only a single bit relative to binary pattern 220 (10010), binary pattern 226 (01010), and binary pattern 228 (11110), etc. In this example, symbols 210 are arranged around circles 230 . 232 . 234 . 236 having radial values or amplitudes of 0.25, 0.50, 0.75, and 1.0, respectively. Those of ordinary skill in the art will recognize that the symbol/station locations may be assigned to achieve desired system performance and that the signaling strategy is generally independent of the particular location assignment and associated digital data/binary pattern. Similarly, although the constellation diagrams illustrated in FIGS. 1 and 2 have generally symmetrically, regularly spaced stations, an asymmetric configuration may be used depending on the particular application and implementation. HIGO. 3 illustrates a representative virtual periodic waveform having a designated period of 360 degrees in this example, in addition to phase-shifted versions of the waveform for use in generating voltages or currents representing digital data in various embodiments of a system or method according to the present disclosure. In the representative embodiment illustrated in FIG. 3. periodic waveform 300 represents a VSW having an amplitude of 1.0. Waveforms 310 . 320 are shown to illustrate the same waveform 300 phase shifted by 120 and 240 (or equivalently 120), respectively. Those of ordinary skill in the art will recognize that the VSW may have a different designated period, or may be implemented by a periodic waveform other than a sine wave depending on the particular application and implementation. HIGO. 4 illustrates representative virtual periodic waveforms each having a period of 360 degrees and different amplitudes for use in generating voltages or currents representing digital data in various embodiments of a system or method according to the present disclosure. Waveform 300 corresponds to the VSW of FIG. 3 with an amplitude of 1.0. Waveforms 350 . 370 . and 390 have the same period and phase, but amplitudes of 0.75, 0.50, and 0.25, respectively. Waveforms 300 . 350 . 370 . and 390 may be used to illustrate determination of voltage/current values used to encode station coordinates of a constellation diagram, such as the constellation diagram of FIG. 1. or the constellation diagram 200 of FIG. 2. for example. Las Figs. 5A-5D illustrate representative arrangements for three-conductor signaling clusters 525 for I/O signaling using multi-phase wired signaling according to various embodiments of the present disclosure. HIGO. 5A illustrates a representative embodiment having a signaling cluster 525 with three conductors 510 . 520 . and 530 in a generally vertical arrangement. Conductors 510 . 520 . and 530 may be implemented by single or multi-stranded insulated wires, or may be implemented as conductive traces on a circuit board or within an integrated circuit, for example. HIGO. 5B illustrates conductors 510 . 520 . and 530 in a generally planar arrangement positioned between generally parallel planes 550 and 560 of an integrated circuit chip or circuit board layers, for example. As previously described, one or more signaling clusters 525 may be positioned between conductive planes or layers 550 . 560 that may be implemented as a voltage plane of generally constant potential, or ground plane, to reduce or eliminate radiated emissions. HIGO. 5C illustrates an alternative arrangement of conductors 510 . 520 . and 530 with a ground conductor 540 . HIGO. 5D illustrates a similar arrangement of conductors 510 . 520 . and 530 without a ground wire or conductor. Those of ordinary skill in the art will recognize that the shape, size, and number of conductors may vary depending on the particular application and implementation to provide desired system characteristics. Wires or other conductors may be insulated or otherwise separated from one another and may be generally parallel, or may be twisted with a specified twist ratio. Various embodiments according to the present disclosure use impedance matched conductors to provide desired operating characteristics as described in greater detail herein. Operation of a representative embodiment of a multi-phase wired signaling strategy having three conductors, such as conductors 510 . 520 . and 530 . is described with reference to FIGS. 2-5. One of the conductors, such as conductor 510 is arbitrarily designated as a base/reference conductor denoted Q and is used to transmit voltage/current values generated/determined using a periodic waveform, such as a VSW. In the embodiments illustrated, the Q conductor has voltage/current values corresponding to a 0 phase shifted VSW, such as VSW 300 . One of the remaining conductors 520 is arbitrarily designated as R for purposes of this example, representing the same virtual sine wave 300 . but at a location determined by the period/n, where the period is 360/3 or 120 phase shifted along the wave, which can also be represented by phase shifted VSW 310 . The remaining conductor 530 is designated as S, representing the same virtual sine wave 300 . but at a location 240 phase shifted along the waveform, which can also be represented by phase-shifted waveform 320 . por ejemplo. For printed circuit board (PCB) layouts, the three conductors can be oriented as planar, vertical, or triangle cross-sections, with typical arrangements illustrated in FIGS. 5A-D and described above. Similar to differential pair implementations, controlled impedance and impedance matching across conductors of a signaling cluster is desired to manage radiated emissions, power, and other performance characteristics. In translating or encoding the constellation stations or coordinates as illustrated in FIG. 2. for example, to voltage/current values to apply to the designated QRS conductors 510 . 520 . and 530 . respectively, a table like the one below may be used. The table values may ultimately be represented or implemented by an appropriate selection of circuit component values and arrangement in the transmit/receive driver circuitry. The table below illustrates representative QRS voltage coding for a voltage-based tri-phase (three conductor) signaling strategy (system or method) with 32 stations or symbols. For each station, the driver circuitry applies voltages associated with the two-dimensional (in this example) coordinates to corresponding QRS conductors in the group or cluster of three conductors representing values of the VSW at appropriate phase offsets. For example, the Q conductor directly encodes the VSW amplitude/phase as a current or voltage value associated with the selected station/symbol in the constellation. The R conductor encodes the VSW amplitude/phase for a position that is phase shifted (advanced or retarded) by 120. The S conductor encodes the VSW amplitude/phase for a position phase shifted by 120 relative to the Q and R conductors, i. e. retarded by 120 or advanced by 240. In operation, each symbol/station 220 includes associated digital data, represented by multiple-bit binary pattern 222 . and an assigned two-dimensional coordinate/location lt1,0gt representing amplitude (1.0) and phase (0) of a periodic waveform 300 having a period of 360 degrees in this embodiment. As shown in the lookup table below and in FIGS. 3 and 4. the amplitude and phase is converted to a first corresponding voltage (or current) based on the value of the periodic waveform as represented by point 350 and applied to a first conductor 510 (Q). The amplitude and phase is converted to a second corresponding voltage (or current) based on a value of the periodic waveform 300 phase shifted by 120 degrees as represented in the table below and by point 360 of FIG. 3. This voltage (0.866025) is applied to the second conductor 520 (R) by the driver circuitry. The amplitude and phase is converted to a third corresponding voltage (or current) based on a value of the periodic waveform 300 phase shifted by 240 degrees as represented in the table below and by point 370 of FIG. 3. This voltage (0.866025) is applied to the third conductor 530 (S) by the driver circuitry. As those of ordinary skill in the art will appreciate, the voltages (or currents) are applied to the QRS conductors at substantially the same time, i. e. within a symbol window, as determined to provide appropriate margin for a synchronization clock signal provided to the transmit/receive driver circuitry as previously described. QRS values for a tri-phase wired 32-symbol constellation as shown in FIG. 2 are represented by the periodic waveforms illustrated in FIG. 4 and listed in the lookup table below. As previously described, the constellation station locations/coordinates may be assigned to achieve particular performance characteristics. However, in this representative embodiment using the constellation diagram 200 of FIG. 2. stations are symmetrically spaced at four substantially equal intervals of 0.25, 0.50, 0.75, and 1.0. This arrangement facilitates scaling to other voltage/current ranges appropriate for a particular PCB, IC, or other wired application based on the associated board/chip/system voltage. The stations/symbols are substantially equally spaced around the 360 circle, at 45 intervals in this example, although other arrangements are possibly and within the scope of the invention. This representative arrangement provides eight radials and four positions on each radial for a total of 32 stations/symbols in the constellation, for a five-bit coding system using three conductors between transmitting and receiving components. Those of ordinary skill in the art will appreciate that if negative amplitudes are used, the phase coordinates should be selected such that a negative amplitude does not map onto another phase radial that is 180 degrees from the current one. The QRS values listed in the table below are generally illustrated by the periodic waveforms of FIG. 4 with waveform 300 having an amplitude of 1.0, waveform 350 having an amplitude of 0.75, waveform 370 having an amplitude of 0.5, and waveform 390 having an amplitude of 0.25. The QRS values for any amplitude/phase station coordinate/location may be obtained as previously described and illustrated with respect to FIG. 3. As indicated in the table below, the voltages (or currents) associated with each symbol sum to substantially zero. As previously described, the phase arrangement for any given constellation can be arranged to provide desired separation and associated detectability for a particular application or implementation. Those of ordinary skill in the art may recognize that the multi-phase signaling strategy described above may facilitate auto-alignment of voltages between transmitters and receivers. For example, if a transmitter were sending to a receiver where only the ground is shared, the receiver could auto-align by determining the absolute min/max voltages on the Q wire and using those to scale the R amp S wires to recover the constellation. In addition, because the signaling strategy is modeled after the ubiquitous tri-phase power transmission system, the steady-state power at every station is nearly identical for a particular amplitude if the design has controlled impedance. The multi-phase signaling strategy according to various embodiments of the present disclosure provides a number of advantages. For example, while a transition from one station/symbol to another station may produce little or no voltage/current change in one wire of the signaling cluster, one or more of the other wires experiences a larger-range digital-like voltage swing, which improves noise margin and reduces bit error rate. In addition, external transients tend to couple equally onto all wires of a signaling cluster, which still permits decoding a station and associated digital data based on the relative values between the various wires rather than absolute individual values. Using the differential voltage/current values between pairs of conductors within a signaling cluster also provides common-mode noise rejection while still providing a good set of detection values as demonstrated by the examples below. Furthermore, because the positions/locations/coordinates of the stations in the constellation are arbitrary, they may be positioned to achieve specified voltage/current ratios that are easier to generate and decode, rather than using forced equal spacing. In addition, the nearly identical power-per-station for a given amplitude, indicates that the signaling strategy may be able to achieve constant power during transitions, achieving a digital transmission system with near zero switching emissions. Those of ordinary skill in the art will appreciate that traditional system analysis tools, such as the eye diagram associated with differential pairs is no longer directly available. Furthermore, many possible encodings exist where no station/symbol has the full amplitude value. However, as long as the QRS stream visits each station with substantially the same probability, recovery of the constellation and the associated digital data is possible even with severe signal drop down a transmission line, similar to the manner used in conventional RF N-QAM systems. Transmission-Side Implementation for Multi-Phase Wired Signaling FIG. 6 is a diagram illustrating a representative embodiment of circuitry for a transmission device for use in multi-phase wired signaling according to the present disclosure. Circuitry 600 implements a standard R-2R constant-current switch ladder to generate a corresponding voltage which is applied to one of the signaling conductors through a precision voltage follower/inverter. In the representative embodiment of a transmission device illustrated in FIG. 6. V r is connected to an internal reference voltage, and the voltage follower/inverter 610 directly drives the associated conductor 612 by applying the corresponding voltage to the conductor. A look-up table or similar device drives the switching bits 620 to select the voltage appropriate for the QRS wire being driven as previously described. One advantage of an R-2R ladder as illustrated in FIG. 6 is that the various switches 630 controlled by bits 620 can be implemented as make-before-break switches (e. g. MAX4625 analog switches available in 6-pin packages from Maxim, Sunnyvale, Calif.) which allows constant current flow without switching transients at the driving side. Those of ordinary skill in the art will recognize that the switching bits 620 are selected to generate a suitable number of voltages as required by the number of symbols and the constellation coordinate assignments. For example, if using the table above in a 32-symbol system, Vr would be connected to 1, and the number of switching bits 620 would be selected to give reasonable approximations of the different Q, R, and S values from the table. As previously, described, the representative embodiment illustrated facilitates scaling to various system voltages. HIGO. 7 illustrates another representative embodiment of circuitry for a transmission device using CMOS transmission gates for multi-phase wired signaling according to the present disclosure. In the embodiment illustrated in FIG. 7. fixed voltage sources 710 . 720 . 730 . and 740 are selectively switched by CMOS transmission gates 750 to select the appropriate voltage source and apply the corresponding voltage to conductor 760 . As such, voltages represented by V 0 . V 3 (readily extended to an arbitrary number of voltages) corresponding to the Q, R, or S values previously described are connected to a respective CMOS transmission gate S 0 . S 3 . The desired voltage may be selected by using a decoder to select one specific transmission gate to enable. A design such as this one would internally generate a voltage reference tree that contains all of the required voltages in the Q, R, and S columns in the table above. The representative implementations of FIG. 6 and FIG. 7 permit reasonable accuracy in generating a corresponding voltage, V out . for driving each of the Q, R, and S conductors. Of course, those of ordinary skill in the art may recognize various other implementations to apply a selected voltage to the conductors in a signaling cluster consistent with the present disclosure. In operation, the circuitry illustrated in the embodiments of either FIG. 6 or FIG. 7 may be used to convert a first amplitude and phase of a periodic waveform to a first corresponding voltage and apply the first corresponding voltage to a first at least one of the plurality of conductors in a signaling cluster. Similarly circuitry may be used to drive each of the n conductors in a signaling cluster such that each stage or section is associated with a particular conductor and operates to convert the first amplitude and first phase to a corresponding voltage based on the amplitude of the periodic waveform phase shifted by mperiod/n degrees relative to the first phase, where m is indexed from one to (n1). As previously described, each conductor in the group of conductors of a signaling cluster may be implemented by two conductors of a differential pair. As such, a voltage (or current) determined for the first conductor would be applied to Q, for example, with the inverse voltage (or current) applied to a second conductor Q. Similarly, the voltage (or current) determined for each of the remaining n1 conductors along with an associated inverse voltage (or current) would be applied to a corresponding pair of conductors. While this implementation requires twice as many conductors, it still reduces the number of conductors required relative to various conventional signaling strategies. In addition, this implementation facilitates use of signaling strategies according to the present disclosure with existing networking infrastructure, such as used in Ethernet applications, for example. Receive-Side Implementation for Multi-Phase Wired Signaling FIG. 8 is a diagram illustrating a representative embodiment of a receiver/detector device including circuitry for multi-phase wired signaling according to the present disclosure. Those of ordinary skill in the art will recognize that there are many possible strategies for decoding specific voltages or currents on the conductors within a signaling cluster according to the present disclosure. For example, high-impedance comparators can be used to quickly determine an approximate voltage/current of an associated conductor. A precise determination of the voltage/current is generally not required in a digital signaling strategy as disclosed here. Another approach would use low-bit flash analog-to-digital (ADC) convertors to quickly determine the voltage/current values. While comparing each conductor independently to a series of references/thresholds may also be suitable in a limited number of applications, this approach is more susceptible to common-mode noise spikes coupled onto the conductors. As such, various embodiments according to the present disclosure use a differential voltage/current comparison of one or more pairs of conductors within a signaling cluster to multiple thresholds/reference values. HIGO. 8 illustrates one embodiment of circuitry for a receiving device that may be used to generate a differential voltage between a pair of conductors of a signaling cluster. Circuitry 800 operates as a differential amplifier or differential voltage follower when resistor values for R 1 . R 2 . and R 3 are substantially identical. A tri-phase wired signaling system as described above would include three such differential amplifiers 800 to generate the differences for QR, RS, and SQ pairs. For example, in the first amplifier, conductor Q connects to V 2 and conductor R to V 1 such that V out generates the differential voltage values in the QR column of the above table. In the second amplifier, conductor S connects to V 2 and conductor Q connects to V 1 . such that V out produces the differential voltage values in the SQ column of the above table. In the third amplifier, conductor R connects to V 2 and conductor S connects to V 1 . such that V out produces the differential voltage values in the RS column of the above table. Note that QR, RS, and SQ also sum to zero. Any deviation from zero indicates errors in one or more of Q, R, S, and can be used to adjust calibration for robustness. The differential voltage values of the QR, SQ, and RS columns in the above table may be used to determine comparator values which can uniquely identify a bit encoding based on the values from the three differential amplifiers. For example, in the embodiment illustrated in the table of FIG. 10. the following 24 reference/threshold comparator voltages are selected: 1.7, 1.55, 1.4, 1.25, 1.1, 0.95, 0.8, 0.65, 0.5, 0.35, 0.2, 0.05, 0.05, 0.2, 0.35, 0.5, 0.65, 0.8, 0.95, 1.1, 1.25, 1.4, 1.55, and 1.7. HIGO. 9 is a diagram illustrating a representative embodiment of circuitry for comparing differential voltages to a plurality of thresholds and generating a binary match pattern for a receiver/detector device for multi-phase wired signaling according to the present disclosure. Circuitry 900 includes a bank of comparators 930 that operates to compare the differential voltages or currents between at least one pair of conductors within a signaling group. In this example, differential voltages associated with the first and second conductors (QR), third and first conductors (SQ), and second and third conductors (RS) are compared to associated reference values or thresholds 920 to generate match bits 940 that form a binary match pattern used to decode the digital data. Match bits 940 (M 0 . M 3 ) create a digital representation or estimate of the value on the given differential output. In general, it is possible to obtain a unique set of detection values or match pattern using less than the number of symbols of the signaling strategy. Stated differently, detection can be accomplished with a number of thresholds or comparators that is less than the number of permutations of the multiple-bit binary pattern. In the representative embodiment described above, the five-bit binary pattern includes 32 permutations or symbols that are detected using 24 reference/threshold comparators, although a smaller or better optimized number may be possible depending on the particular application and implementation. Although one bank of comparators 930 having four comparators is illustrated in FIG. 9. actual implementations may include a dedicated bank of comparators 930 for each pair of conductors of the signaling cluster or group that are used in a particular application, with each bank having a number of comparators less than the number of symbols in the signaling strategy. The number of pairs of conductors used may be selected to achieve desired performance characteristics for a particular application or implementation. For example, as described and illustrated in greater detail with respect to one representative embodiment below, a four-conductor signaling cluster provides six available pairs with only four of the pairs selected. In a representative tri-phase signaling strategy with three signaling conductors, a separate bank of comparators 930 may be provided for each differential voltage pair 910 corresponding to the differential voltages QR, SQ, and RS. Similarly, comparator bank 930 would include a comparator for each selected threshold or reference voltage 920 . In this example, a bank of 24 comparators would be used, only four of which are illustrated in FIG. 9. Each comparator 930 compares the voltage (QR, SQ, or RS) on one input to an associated threshold (V 0 - V 3 ) to generate a corresponding match bit (M 0 - M 3 ) when the input voltage exceeds the threshold. The match bits 940 create a match pattern or match set as illustrated in the table above. As such, circuitry as illustrated in FIG. 9 can be used to generate a binary match pattern for each selected pair of conductors with each bit of the binary match pattern associated with one of the plurality of thresholds 920 . The binary match pattern is then used to determine the corresponding digital data or unique multiple-bit binary pattern. In one embodiment, the maximum and minimum number of asserted bits in the binary match pattern of all of the pairs of the conductors may be used to determine the corresponding digital data, although other techniques may also be used as described in greater detail below. Las Figs. 10A-10C illustrate operation of a system or method for decoding data in response to received differential voltages/currents in a poly-phase wired signaling strategy having three signaling lines according to various embodiments of the present disclosure. As previously described, each signaling line may be implemented by a single conductor, or may be implemented by two conductors operating as a differential pair. In the latter case, a first conductor of the differential pair has a voltage/current as shown in the table, and the second conductor has the inverse voltage/current. The values in this example correspond to a 32-symbol signaling strategy similar to the embodiment previously described. However, the constellation diagram used in the present example has symbol location/coordinates beginning at a phase of 30 and generally equally spaced at 45 intervals, which results in phases of 30, 75, 120, 165, 210, 255, 300, and 345. In addition, rather than 24 comparator voltages or thresholds, only 12 detection thresholds are used in corresponding banks of 12 comparators for each of the differential selected voltage pairs QR, SQ, and RS. In this representative embodiment, comparator voltage thresholds are: 1.4, 1.18, 1, 0.55, 0.28, 0.05, 0.05, 0.28, 0.55, 1, 1.18, and 1.4. This design results in similar robustness as the embodiment previously described, but reduces the receive-side circuitry by about one-half. As with the previously described embodiment, this embodiment associates digital data represented by the data bits in the table below with corresponding unique two-dimensional coordinates representing amplitude and phase of a periodic waveform having a period of 360 degrees. The amplitude and phase are converted to a first corresponding voltage and applied to a first signaling line, corresponding to a first conductor or differential pair (Q) as shown in the table of FIG. 10 A. Similarly, the amplitude and phase are converted to a second corresponding voltage based on a value of the periodic waveform phase shifted by 120 degrees relative to the amplitude and phase, with the second voltage applied to a second signaling line implemented by a conductor or differential pair of conductors (R) as shown in the corresponding column labeled R(120). Likewise, the amplitude and phase are converted to a third corresponding voltage based on a value of the periodic waveform phase shifted by 240 degrees (or 120 degrees) relative to the amplitude and phase and applied to a third signaling line implemented by a conductor or differential pair (S) as represented by the values in the column labeled S(120). As illustrated by the table of FIG. 10 A. the first, second, and third voltages for a particular symbol sum to substantially zero. The differential voltages for each pair of signaling lines (QR, SQ, and RS) is compared to a plurality of thresholds, (12 in this example) to decode the associated digital data word in the column labeled Bits of FIG. 10B. As indicated in the table, the digital data comprises a multiple-bit binary word having n bits (5 in this example) and the number of thresholds (12) is less than 2 n or 32. FIG. 10B illustrates operation of three banks of 12 comparators each used to generate match patterns and decode the associated multiple-bit data words. The values from the bank of comparators 930 at the receiver attached to the QR differential voltage (or current) are represented by the match pattern in the column labeled QR Match Set. Similarly, the values for the comparators attached to the SQ differential voltage (or current) are represented by the match pattern data in the column labeled SQ Match Set. Likewise, the values for the comparators attached to the RS differential voltage (or current) are represented by the match pattern data in the column labeled RS Match Set. Each of the match patterns in the Match Set columns includes asserted bits, represented by 1s in this embodiment, and/or non-asserted bits, represented by 0s in this embodiment, based on the asserted match bits 940 for the thresholds or voltages exceeded or matched by the differential voltage associated with a particular received symbol/coordinate. Values in the column labeled qr1 represent the number of asserted bits or 1s in the QR match set. Values in the column labeled sq1 represent the number of asserted bits or 1s in the SQ match set. Values in the column labeled rs1 represent the number of asserted bits or 1s in the RS match set. Values in the column labeled Max represent the maximum number of asserted match bits (1s in this example, although the inverse logic is equally applicable) across all of the selected pairs of conductors, QR, SQ, and RS in this example. Similarly, values in the column labeled Min represent the minimum number of asserted match bits (1s) for all of the selected pairs of signaling lines (single conductors or differential pairs) in the signaling group or cluster. The table of FIG. 10C provides a sorted list of values for qr1, sq1, and rs1. As illustrated in the tables of FIGS. 10A-10C. the n-tuple or triplets formed by ltqr1,sq1,rs1gt entries are unique across all 32 rows. This permits directly mapping to a specific bit pattern or data word when decoding the received signal based on the number of asserted (or non-asserted) bits in the match pattern. Alternatively, the maximum and minimum number of asserted (or non-asserted) bits may be used to decode the received signal. While there are multiple rows where the same Max/Min values exist, there is always a unique triplet or n-tuple representing the number of asserted bits in each match pattern associated with a signaling line pair that may be used to uniquely identify the associated bit pattern or data word for the otherwise ambiguous Max/Min combinations. As such, Max/Min values may be used in combination with the number of asserted (or non-asserted) bits to decode the signal and uniquely identify an associated bit pattern or data word. Of course, the comparator thresholds and/or number of thresholds may also be selected such that the Max/Min n-tuple or pairings are unique across all symbols, if desired, such that Max/Min could be used to uniquely identify a particular data word or bit pattern. As also illustrated in the table of FIG. 10B. the column labeled Del includes values analogous to conventional eye spacing for detection of the given row using the difference between the maximal 1s span and the minimal 1s span for that row. The spacing is based on the average spacing of the selected comparator voltages/thresholds, which in this example are approximately 0.15 volt per comparator. Similarly, the column labeled Del - includes values analogous to the eye spacing if the maximal span is just over the last 1 comparator detection threshold, while the minimal span is just under the first 0 comparator threshold, which reduces the eye by about 0.15 in this example. As illustrated in the table of FIG. 10B. for this example, there is at least 0.15 volt separation for the worst case eye values and typically 0.3 volt separation, which is readily detectable in a digital system using common-mode noise rejection as in this approach. A 2-Bit-Per-Transition Tri-Phase Example In another embodiment of a wired 4-symbol multi-phase signaling strategy, a simpler design achieves 2-bits-per-transition in a constant amplitude four-station strategy. A periodic waveform implemented by a VSW having an amplitude of unity and phases of 0, 90, 180, and 270 may be used to generate the voltages and bit encodings as illustrated in the following table. From this table it can be readily seen that using three wires and four states, it is trivial to decode each of the four states, with significant noise margin from state to state and also within a given state. When the RS differential voltage is zero (for encodings/digital data of 01 and 11), for example, the QR and SQ differential voltages readily distinguish between the two and eliminate any ambiguity. This simple encoding is readily implemented in both the transmit device and the receive device, and eliminates a wire/conductor compared to a conventional 2-bit differential pair system. Furthermore, this embodiment retains the constant-power-per-bit and noise immunity of a conventional differential pair system, while reducing the number of conductors by 25. Because the I/O is generally the limiting factor in modern high-speed designs, the moderate additional circuitry to encode and decode the data using this signaling strategy will be more than offset by the savings in chip area required for I/O bond-pads and wire connections in many applications. A 5-Bit-Per-Transition Quad-Phase Example A common wiring system known as Star-Quad consists of a twisted quartet of wires. Another embodiment of the present invention can be used over such wiring to achieve significant bandwidth improvement over an equivalent wiring of two twisted pairs carrying two standard differential binary signals. Operation of this embodiment is illustrated and described with reference to FIGS. 11A-11C. In this embodiment, a 32-symbol constellation diagram is used with each station assigned one of four amplitudes of 0.25, 0.5, 0.75, and 1.0 and one of eight phases corresponding to radials spaced at thirty degrees as in the previous embodiment. Encoding is performed using four virtual periodic waveforms each having different amplitudes, which correspond to the amplitudes used in the constellation diagram in this example, but may be assigned or scaled based on the system voltage/current levels as previously described. The virtual periodic waveforms are then used to determine a corresponding voltage (or current) to be applied to an associated signaling line, which may be implemented by a single conductor or by a differential pair as previously described. Each voltage (or current) value is determined based on the value of the periodic waveform at a reference point, and then phase shifted by 90 degrees (R), 180 degrees (S), and 90 degrees (T) analogous to the previously described embodiments. The four signaling lines (Q, R, S, and T) are used to generate four differential values (QR, RS, ST, and TQ) corresponding to at least one selected signaling line pair. Those of ordinary skill in the art will recognize that the four signaling lines (Q, R, S, and T) have six available signaling line pairs (QR, QS, QT, RS, RT, and ST). One or more signaling line pairs may be selected for use in generating the differential values depending on the particular application and implementation. In the representative embodiment illustrated in FIGS. 11A-11C. comparator values/voltages of 1.4, 1.18, 1.0, 0.7, 0.4, 0.1, 0.1, 0.4, 0.7, 1.0, 1.18, and 1.4 result in the match pattern data represented by the match sets illustrated in FIG. 11B. Analogous to the three-wire embodiment, the sum of QR, RS, ST, and TQ is zero, and the 4-tuple or quartet ltqr1,rs1,st1,tq1gt is unique for each bit encoding as illustrated by the sorted table entries of FIG. 11C. Using the same number of wires as two differential pairs, five bits are transmitted in the same amount of time as two bits with conventional differential signaling. Las Figs. 12 and 13 are diagrams illustrating operation of various representative embodiments of a system or method for digital signaling according to the present disclosure. Those of ordinary skill in the art will recognize that the functions represented in the diagrams may be performed by various types of devices, including software, firmware, and/or hardware devices. Depending upon the particular application and implementation, various functions may be performed by circuitry implemented using discrete components and/or integrated circuit components. As such, the various functions may be performed in an order or sequence other than illustrated in the Figures. Similarly, one or more steps or functions may be repeatedly performed, or omitted, although not explicitly illustrated. As previously described, reference to a conductor should be understood to include a signaling line that may be implemented by a single conductor, or by a pair of conductors functioning as a differential signaling pair. As generally represented by block 1210 . a system or method for multi-phase digital signaling includes associating digital data (represented by a unique multiple-bit binary pattern, for example) with corresponding unique n-dimensional coordinates for each of a plurality of binary patterns. The coordinates may represent selected or assigned symbol locations of a constellation diagram, for example. In one embodiment, associating digital data includes assigning n-dimensional coordinates that maximize distance between adjacent pattern coordinates within an associated voltage or current range of the integrated circuit chip. The system or method includes converting each coordinate of the n-dimensional coordinates to a corresponding voltage or current as represented by block 1212 . The system or method may optionally include monitoring a series of sequential coordinate values associated with each conductor as represented by block 1214 and modifying the coordinate values to adjust at least one of DC balance, radiated emissions, and transition density associated with the series of sequential coordinate values before converting each coordinate to a corresponding voltage or current as generally represented by block 1216 . Modifying the coordinate values may include encoding a stream of coordinates associated with each signaling line using a line code before converting the coordinates to corresponding voltages or currents. As also shown in FIG. 12. the system or method include communicating the multiple-bit binary pattern by applying each voltage or current associated with the n-dimensional coordinates to a corresponding conductor of a group of n conductors, wherein the number n of conductors is less than the number of bits of each multiple-bit binary pattern, as generally represented by block 1218 . As represented by block 1220 . the system or method include decoding the multiple-bit binary pattern associated with the n-dimensional coordinates based on detecting the voltages or currents of the n conductors. Decoding the digital data may optionally include comparing the voltages or currents to a plurality of thresholds to determine a corresponding coordinate value as represented by block 1222 . Likewise, decoding the digital data may optionally include using the n-dimensional coordinates to retrieve an associated unique multiple-bit pattern from a lookup table as represented by block 1224 . The system or method may also include changing the corresponding conductor associated with a particular dimension of the n-dimensional coordinates to alter DC balance across the group of n conductors as represented by block 1226 . As illustrated in the diagram of FIG. 13. in one embodiment a system or method for multi-phase signaling includes associating digital data with corresponding n-dimensional coordinates or locations wherein the n-dimensional coordinates are two-dimensional coordinates representing amplitude and phase of a periodic waveform as generally represented by block 1310 . As previously described, the amplitude and phase coordinates are converted to a first voltage or current that is applied to a first signaling conductor as represented by block 1312 . The system or method then includes generating (n1) voltages or currents each corresponding to values of the periodic waveform at phases of about 360/n degree intervals as represented by block 1314 . As those of ordinary skill in the art will recognize, the first and (n1) voltages or currents are applied substantially simultaneously to corresponding conductors for each symbol to transmit or communicate the digital data. Detection and decoding of transmitted digital data begins by generating differential voltages or currents for at least one pair of the conductors as represented by block 1316 . The system or method continue by comparing each differential voltage or current to a plurality of thresholds to select the corresponding unique multiple-bit binary pattern (digital data) as represented by block 1318 . In one embodiment, the number of thresholds is less than the number of permutations of the multiple-bit binary pattern, i. e. for a 4-bit binary pattern the number of thresholds would be less than 16. As also shown in the diagram of FIG. 13. detecting the transmitted n-dimensional coordinates and associated digital data may include generating a binary match pattern for each of the at least one selected pair of the conductors with each bit of the binary match pattern associated with one of the plurality of thresholds as represented by block 1320 . The system or method may also include determining a corresponding unique multiple-bit binary pattern (digital data) based on a number of asserted bits in the binary match patterns of all of the selected pairs of the conductors as represented by block 1322 . In one embodiment, the maximum and minimum numbers of asserted bits associated with the selected pairs of conductors within a particular symbol period are used to determine a corresponding digital data word. Alternatively, the number of asserted bits in match patterns associated with each selected pair is used to differentiate between otherwise ambiguous maximum/minimum values. This may include accessing a look-up table indexed by the number of asserted bits and/or the maximum and minimum number of asserted bits with the output corresponding to the associated digital data (unique multiple-bit pattern). Those of ordinary skill in the art will recognize that the embodiments of the present disclosure demonstrate that the multi-phase signaling strategy described, with little or no optimization, provides a robust mechanism for decoding five bits or two bits per transition over three conductors. This provides a significant improvement relative to conventional differential pair signaling. For example, in a conventional different pair strategy with a single bit per transition, six conductors are used to transmit three bits per transition. In contrast, using a multi-phase signaling strategy according to the present disclosure enables transfer of ten data bits per transition in a five-bit-per-symbol implementation, or four data bits per transition in a two-bit-per-symbol design, for a bit density increase of over 300 in the five-bit strategy and a bit density increase of 33 in the two-bit strategy. This comes at the expense of a moderate amount of additional circuitry for encoding and decoding. For IC chip implementations, every differential pair already has effectively a driver per I/O conductor. For the multi-phase signaling embodiments described above, the resistors needed to form the R-2R ladder switches, or to create the desired voltage values for the CMOS pass-gate implementation require very little area. Pass-gates are similarly small, low-current devices, so there is minimal impact on the transmit side. On the receive side, the representative example uses one differential amplifier per conductor pair, which is analogous to the differential receiver in a conventional differential pair signaling strategy. As such, the representative embodiments of a signaling strategy according to the present disclosure result in a 50 increase in the number of amplifiers. For example, in the six-wire comparison described above, nine amplifiers would be used in the multi-phase signaling strategy with one amplifier for each pair of conductors as compared to only six for a conventional differential pair strategy. This would require about 50 more IC chip area to accommodate the additional amplifiers. The bank of comparators associated with each differential amplifier is unique to the multi-phase signaling embodiments. In addition, the binary match sets may use a simple look-up table or other device with 32 entries to provide the 32-to-5 bit lookup symbol decoding function and identify the corresponding five-bit digital data value. However, all of this circuitry is fast and small and should not be a significant deterrent to widespread adoption. Furthermore, optimization of the threshold match voltages can produce a design that uses significantly fewer comparators. In an alternative embodiment suitable for applications where more noise or EM interference is present, the direct-match function of the comparators and pattern matching bits can be replaced by a statistical similarity match similar to PRML (Partial Response Maximum Likelihood) techniques to extract the most probable symbol and associated 5-bit data, for example. The resulting design with the five-bit-per-transition approach provides a system which is capable of matching existing differential-pair transmission speeds, but provides over three times the number of bits per I/O pad on an integrated circuit. With the two-bit-per-transition approach, a 33 increase is achieved. With a small amount of rework, a 10 gigibit-per-second design becomes a 50 gigibit-per-second design at the same clock speeds. A gigabit Ethernet readily becomes a five gigabit network. A 15-bit differential bus, with 30 wires, capable of transferring 15 bits per transition using conventional differential signaling, becomes a set of 10 tri-phase signaling groups or clusters (30 wires), each transferring five bits in this example, resulting in a capacity of fifty bits per transition. Conversely, the same 15-bit bus with 30 wires could be replaced with three tri-phase groups requiring only nine wires for 15 bits instead of the thirty required for differential signaling, such that the remaining 21 wires and I/O pads are available to expand the chip design. Furthermore, with additional precision on the voltages and the decoding, the constellation size could readily be increased beyond the demonstrated 32 stations. Tri-phase wired signaling according to the present disclosure retains many of the advantages associated with conventional differential pair signaling, such as constant power (for a given amplitude), for example. In addition, a driving amplifier design that preserves constant power across amplitude changes can be created, providing a significant reduction in switching transients associated with data transfer from one integrated circuit to another. Backplanes and card connectors, also a bottleneck source, could be redesigned to use wire triplets, with either significant reduction in connector pin count, significant increase in bandwidth over the same size connector, or a combination of both. Those of ordinary skill in the art will recognize that use of multi-phase wired signaling according to the present disclosure at slower switching speeds, with each wire representing one dimension in an N-dimensional constellation, and each dimension represented by K values, an N-wire system can carry K N values instead of 2 N values provided by existing digital systems. If K is eight (2 3 ), for example, the N-wire capacity becomes 2 3N on the same N-wire bus. An 8-wire bus can now carry 2 24 values instead of only 2 8. Existing differential-pair style connectors and backplanes can still be used, with slower switching speeds due to the increased bit carrying capacity over the same conductors. A 10 gigabit design requiring a 64-bit bus clocked at 156.25 MHz could be redesigned with K8 and a voltage range of 2 to 2V (2.0, 1.43, 0.857, 0.286, 0.286, 0.857, 1.43, 2.0) so that each pair carries three bits per transition instead of a single bit. The same 10 gigabit rate could be achieved with either of the wires at the same clock rate, or the same number of wires could be used and the clock rate reduced by to about 53 MHz, significantly reducing radiated emissions. As can be seen by the embodiments illustrated and described above, systems and methods for wired signaling according to the present disclosure may provide a number of advantages and facilitate a substantial increase in the input/output capacity in a number of applications including integrated circuits, such as microprocessors, without consuming significant on-chip resources or power budgets. Likewise, embodiments according to the present disclosure may provide an order of magnitude or more increase in I/O data rates over chip-to-chip busses without an increase in pin count or significant increases in power budget. As such, embodiments of the present disclosure facilitate a significant increase in chip-to-chip or component-to-component available bandwidth, with an associated significant increase of the processing capability of microprocessors and other integrated circuits. The communication of multiple bits of information using a single symbol represented by n-dimensional coordinates facilitates a reduction in the signal edge rates and a corresponding reduction in radiated emissions. Embodiments that permit only one wire of a signaling group or cluster to change state at a time may also reduce radiated emissions. Embodiments may include a ground wire or conductor associated with each signaling cluster to reduce or eliminate coupling of signals between adjacent signaling clusters. Using signaling strategies according to the present disclosure addresses the I/O bottleneck encountered by parallel high-speed systems and provides a path forward that will limit the influence of I/O pad size from being the integrated circuit bottleneck for the foreseeable future. While exemplary embodiments are described above, it is not intended that these embodiments describe all possible forms of the invention. Rather, the words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the invention. Additionally, the features of various implementing embodiments may be combined to form further embodiments of the invention. Similarly, while the best mode has been described in detail with respect to particular embodiments, those familiar with the art will recognize various alternative designs and embodiments within the scope of the following claims. While various embodiments may have been described as providing advantages or being preferred over other embodiments with respect to one or more desired characteristics, as one skilled in the art is aware, one or more characteristics may be compromised to achieve desired system attributes, which depend on the specific application and implementation. These attributes may include, but are not limited to: cost, strength, durability, life cycle cost, marketability, appearance, packaging, size, serviceability, weight, manufacturability, ease of assembly, etc. The embodiments described herein that are characterized as less desirable than other embodiments or prior art implementations with respect to one or more characteristics are not outside the scope of the disclosure and may be desirable for particular applications. Technical Learning Home Fieldbus amp Device Networks While the network technologies described so far are typical for business information systems, they are converging with industrial instrumentation and control systems. Industrial plants have used information technology (IT) for years, but with open IT standards, faster computers, emerging software, and demand for integrated information by all segments of an industrial enterprise (accounting, engineering, operations, maintenance, and management), industrial networks are merging right into enterprise-wide IT solutions. PLCs and distributed control systems (DCSs) are offering Ethernet/ TCP/IP connectivity so that real-time information on plant processes is readily accessible by any workstation on the network (LAN or WAN), in a client-server relationship. A plant manager can watch a graphic display of plant operations in one window while scanning accounting data in another. Object Linking and Embedding (OLE) and Dynamic Data Exchange (DDE) can merge data streams, such as unit cost (from accounting) and production totals (from the plant floor) in one spreadsheet. Internet and intranet browsers running Java or HTML applications access data acquisition and control systems using standard LAN/WAN technologies. Meanwhile, on plant and factory floors, industry has developed its own range of fieldbus or device-level networks for linking control devices with increasingly intelligent instrumentation. As the terms have evolved over the past several years, device networks typically embrace those optimized for discrete manufacturing automation, while fieldbus connotes more process-oriented instrument networks. On the discrete side, the emphasis is on high-speed transmission of typically smaller information packets. Process fieldbuses, on the other hand, sacrifice speed for more secure transmission of larger information packets. Intrinsically safe capabilities also are prerequisite for many process applications. An exhaustive comparison of the 20-some device and fieldbus protocols currently available is beyond the scope of this volume. However, an examination of two leading alternatives, the Profibus family of automation networks and the Foundation process automation protocol, illustrates the essential concepts of both types of networks. The Profibus Family Profibus is a fieldbus and device network technology used primarily in Europe, but gaining worldwide acceptance. The Profibus family follows an open network standard (EN 50 170) with hundreds of vendors supporting a common, interchangeable interface and protocol. Profibus PA-Process Automation. Allows sensors and actuators to be connected on one common bus line, even in intrinsically safe areas. Profibus DP-Factory Automation. Optimized for high speed and inexpensive connectivity (plug and play). Designed for communication between automation control systems and distributed I/O at the device level. Profibus PA-Process Automation. Allows sensors and actuators to be connected on one common bus line, even in intrinsically safe areas. Profibus DP-Factory Automation. Optimized for high speed and inexpensive connectivity (plug and play). Designed for communication between automation control systems and distributed I/O at the device level. Figure 4-10: Profibus Applications Profibus FMS-Automation for General Purposes. Designed for a large number of applications and communications at the cell level. Profibus is basically a serial bus system with which digital controllers can be networked together with master and slave devices over a pair of wires. Masters, or active stations, control the data communication on the bus. They can send messages without an external request by holding bus access rights by way of a token. Slaves, or passive stations, are peripheral devices that may include input/output (I/O) modules, valves, drives, and transmitters. Slaves do not have bus access rights they can only acknowledge received messages or send messages when the master requests one. The Profibus protocol varies with each member of the family (Figure 4-11). Figure 4-11: Protocol Architecture of Profibus Profibus DP uses the physical and data link layers (1 and 2), coupled to a user interface, for fast and efficient data transmission. Layers 3 through 7 are not defined. A Direct Data Link Mapper (DDLM) provides access between the user interface and the data link layer. Application functions are defined in the user interface. The physical layer is defined via the RS-485 or fiber optic transmission technologies. Profibus FMS defines the physical, data link, and application layers. Layers 3 through 6 are not defined. The application layer combines the Fieldbus Message Specification (FMS) and a Lower Layer Interface (LLI). FMS runs the application protocol as well as supporting communication services. The LLI implements communications and provides device-independent access to the Fieldbus Data Link (FDL) at layer 2. Layer 1 is implemented again in RS-485 or fiber optics. Profibus PA is an extension of the Profibus DP protocol for data transmission. Layer 1 (physical) in this standard uses IEC 1158-2, which provides intrinsic safety and power on the bus for field devices. 1158-2 modulates a steady-state 10 mA dc basic current (the bus power) by Manchester encoding a 1779 mA dc signal on top of the basic current. Manchester encoding refers to a signaling technique that produces binary ones and zeroes by transitioning between high and low signals (9 mA dc to -9 mA dc in the 1158-2 case) over an elevated steady-state voltage or current. A high-to-low transition is a one, and a low-to-high transition is a zero. Thus, every bit period has a transition in it, allowing the receiver to synchronize easily with the transmitter. One disadvantage is that it requires twice the bandwidth as straight binary encoding. Profibus DP and Profibus PA can be integrated via a segment coupler. And because Profibus DP and Profibus FMS use the same transmission technology and a uniform bus access protocol, they can be operated simultaneously on the same cable. Foundation Fieldbus The Fieldbus Foundation is a worldwide consortium of manufacturers and industry groups that have designed and manufactured another open fieldbus technology called Foundation. Software and hardware specifications have been written by design and marketing teams, and many products are becoming available that conform to this standard across many different vendors. The Foundation protocol (Figure 4-12) uses layers 1, 2, and 7 (physical, data link, and application layers). Layers 2 and 7 are considered bundled together in a communication stack. Figure 4-12: Foundation Fieldbus Protocal Stack Foundation and Profibus look similar at first. On the physical layer, the main differences are in signaling methods. Foundation offers IEC 1158-2 signaling, like Profibus. Foundation also offers a 31.25-kbps option, as well as 1.0 and 2.5-Mbps options. The 31.25-kbps version uses a Manchester encoding scheme (17710 mA dc into 150 ohm load) that can use existing 4-20 mA twisted pair wiring. With an intrinsically safe IS) barrier, the 31.25-kbps option supports intrinsic safety. The dc supply voltage ranges from 9 to 32 volts, but may be restricted to the barrier rating. Stubs or spurs are allowed, from 1 meter to 120 meters depending on the number of devices on the bus. The 1.0 and 2.5-Mbps options both offer voltage mode signaling. The 1.0-Mbps option also allows current mode signaling. The voltage mode method delivers 17760 mA dc into a 75-Ohm equivalent load, while the current mode signaling method modulates the fieldbus signal on top of a 16-kHz ac power signal. Figure 4-13: Typical Enterprise Network The Foundation communication stack is comprised of layers 2 and 7 in the OSI model. Layers 3 through 6 are not used. The Data Link Layer, or DLL, controls message transmission on the bus through a Link Active Scheduler (LAS). Link Masters and Bridges are used to control and extend the bus. The Fieldbus Access Sublayer (FAS) works with the Fieldbus Message Specification (FMS) to form an application layer, just underneath the user application. The FAS services are described via Virtual Communication Relationships (VCRs). The VCR is like a speed-dial feature on a telephone, used for communicating quickly and easily to another fieldbus device. Three VCR types, Client/Server, Report Distribution, and Publisher/Subscriber are used for operator messages, event notification and trend reports, and data publishing, respectively. The Fieldbus Message Specification (FMS) communicates via data objects and function blocks over the bus. FMS can only use the client/server VCR type. User applications in the Fieldbus protocol use standardized function blocks for I/O engineering unit conversion, and common functions like PID control. Referencias y lecturas adicionales